The use of substrates between the chips has the following disadvantages. They greatly increase the distance between two chips, which leads to a great stack height. They are restricted to relatively great spacings of the contact areas. They cannot be used in parallel processes, for example at wafer level. Additional connecting elements, such as wire bonds or bumps for example, such as wire bonds or bumps for example, must be provided to accomplish the connection between the wiring plane on the chip and the interposed substrate.
The use of solder balls for contacting the substrate is accompanied by further disadvantages. To keep the stack height as small as possible, it is advisable for only very small solder balls to be used. These very small solder balls are usually produced by means of electrochemical (galvanic) depositing on a photostructured surface. Together with the creation of a solder resist layer, this technology requires two additional lithographic steps. Furthermore, solder bumps are not mechanically stable enough, for which reason they have to be subsequently underfilled. Altogether, these disadvantages make the solder bump technology a very expensive technology.
WO 01/75969 discloses a chip with an integrated circuit and a wiring on a surface with metal-coated elevations for electrically connecting the circuit, the elevations comprising an elastic material and respectively having a metallic contact area on their tips and a line path on their sloping side or in their volume, which path is arranged between the contact area and a conductor track.
FIGS. 8–10 are schematic representations of production of an integrated circuit known from WO 01/75969 A1, with a wiring plane with elastic elevations.
With respect to FIG. 8, reference numeral 1 designates a semiconductor chip with a terminal region 19 of an integrated circuit not shown here, which is accommodated in the semiconductor chip. Provided on the semiconductor chip 1 is an insulating layer 7, which has a surface 13, with a through-hole 26 being provided to expose the terminal region 19.
FIG. 9 shows that an elastic elevation 3 with a height h is provided on the surface 13 of the insulating layer 7. Used for example for this purpose is a silicone-based elastic elastomer, which is applied via a perforated stencil to the surface 13 of the insulating layer 7 by a printing process. The stencil (not represented) itself comprises, for example, a perforated metal foil. By setting the viscosity and the composition of the silicone, the form and height h of the elastic elevation 3 can be specifically set.
FIG. 10 illustrates how a metal layer structure is applied to the surface 13 of the insulating layer 7 and to the surface of the elastic elevation 3 and also into the through-hole 26, said metal layer structure connecting the terminal region 19 to a contact area 16 on the tip of the elastic elevation 3 via a conductor track 4 on the insulating layer 7. In this respect it should be noted that the regions 16 and 4 may be structured identically or differently. For example, the contact area 16 may have a greater cross section than the conductor track 4.